Next-Generation Computational Lithography

OPC+ Cloud Platform

Cloud-Based Freeform Mask Correction · GPU-Accelerated OPC for Semiconductor & Photonics

Developed by PAL Lab & NSL Lab · National Yang Ming Chiao Tung University

Cloud Native GPU Accelerated 50× Faster Curvilinear Support
50×Faster than CPU OPC
<2%Load Imbalance
12+GPUs in Public Cloud
GDS/OASISIndustry-Standard Formats
FreeformCurvilinear Mask Support

What Is Optical Proximity Correction (OPC)?

Semiconductor and photonic devices are fabricated by projecting light through a patterned mask onto a photosensitive wafer—a process called photolithography [1]. Because the wavelength of the exposure source is comparable to, or larger than, the minimum feature sizes being printed, optical diffraction causes the projected image to deviate systematically from the intended design: line ends shorten, corners round off, and isolated features may fail to print entirely.

Optical Proximity Correction (OPC) is the pre-distortion technique applied to the mask layout to compensate for these optical and process-induced effects, so that the final printed pattern on the wafer faithfully reproduces the designer's intent. Modern OPC is increasingly realized through Inverse Lithography Technology (ILT)—a full-mask optimization approach that directly solves for the mask shape required to produce a target wafer image [2].

OPC Concept: Target vs. OPC Mask

Figure 1. The target layout (left, without correction) produces a blurred wafer image due to diffraction. The OPC-corrected mask (right) pre-distorts the design so the printed result faithfully reproduces the intended pattern.

Why Is Traditional OPC Insufficient?

Conventional OPC tools rely on CPU-based, rule-driven solvers designed for Manhattan geometries (rectilinear, axis-aligned shapes). They present three fundamental limitations as the industry advances toward photonics and curvilinear CMOS nodes:

LimitationImpact
Speed CPU-bound serial processing makes large-layout corrections extremely time-consuming—often requiring hours per job
Cost & Accessibility Commercial licenses are prohibitively expensive and operation requires specialized expertise, excluding startups and research institutions
Geometry Constraints Photonic integrated circuits and next-generation curvilinear CMOS nodes require freeform mask geometries that traditional tools cannot handle natively—forcing lossy polygonal approximation

Breaking the Barriers of Traditional OPC

OPC+ is a cloud-native, GPU-accelerated platform that democratizes advanced mask correction. By replacing CPU-bound solvers with massively parallel GPU computation and wrapping the entire workflow in an intuitive web interface, OPC+ removes the barriers of traditional tools while extending OPC capabilities to cutting-edge photonic and semiconductor applications [3].

The platform is built around three core principles:

Speed

CUDA Multi-Stream parallelism delivers 50× faster correction than CPU-based solvers. Jobs that previously required hours complete in minutes, enabling rapid design iteration [3][4].

Accessibility

A web-based GUI requires no scripting or deep OPC expertise. Upload a layout, configure scanner parameters, and submit. No hardware investment required—GPU clusters are provisioned on demand.

Generality

Native curvilinear mask support enables OPC beyond digital CMOS, validated on photonic integrated circuits and large-area metasurfaces [5][4].

SEM Validation on Fabricated Devices

The following Scanning Electron Microscope (SEM) images present fabricated device results demonstrating the direct, measurable impact of OPC correction on real photonic structures. All results were obtained from wafers processed at collaborating fabrication facilities.

Line Pattern — Line End Shortening

Without OPC correction, diffraction at the tips of line features causes the printed ends to recede inward, resulting in lines that are shorter than the target design. This line end shortening effect introduces critical dimension (CD) error along the line length axis. OPC pre-compensation extends the mask geometry at line ends so that the fabricated result matches the intended length.

Line pattern without OPC
Without OPC
Line end shortening visible; printed length undershoots target geometry
Line pattern with OPC
With OPC
Line ends accurately reproduced; CD along length axis restored

Figure 2. SEM images of fabricated line patterns. Scale bar: 5 µm.

Ring Resonator — Critical Defect Elimination

For photonic ring resonators, OPC correction is critical to device functionality. Without correction, the coupling gap region fails to open properly—a fatal fabrication defect that renders the device non-functional optically. With OPC, the waveguide geometry is accurately reproduced and the coupling region is fully resolved [5].

Ring resonator without OPC
Without OPC
Critical defect: lower photoresist layer not opened (circled in red)
Ring resonator with OPC
With OPC
Clean fabrication: coupling region fully resolved, device functional

Figure 3. SEM images of fabricated ring resonators. Scale bar: 5 µm (overview), 1 µm (inset).

Metalens — Sub-Wavelength Feature Survival

Metalenses rely on densely packed sub-wavelength nano-structures whose precise geometry determines the phase profile of the device. Without OPC, the photolithography process fails to resolve the smallest features—they are either significantly distorted or lost entirely—compromising the optical function of the device. With OPC, all features are faithfully reproduced after lithography, preserving the intended phase distribution across the aperture [5].

Metalens without OPC
Without OPC
Small features fail to resolve; critical nano-structures lost or severely distorted after lithography
Metalens with OPC
With OPC
All sub-wavelength features fully resolved; phase profile of metalens preserved

Figure 4. SEM images of fabricated metalens structures. OPC ensures survival of all sub-wavelength features critical to device phase control.

Key Features

GPU Acceleration

Leveraging CUDA Multi-Stream image-level parallelism, OPC+ achieves 50× faster mask correction compared to CPU-based methods [3][4].

Cloud-Native Architecture

Built on Kubernetes with elastic resource scheduling. OPC+ dynamically allocates GPU resources across public, private, or hybrid environments. No capital hardware expenditure required.

Native Curvilinear Mask Support

OPC+ natively generates curvilinear masks without polygonal approximation, preserving optical phase and waveguide coupling efficiency in photonic applications [5].

Global Inverse Optimization

Full-mask ILT with contour-based L2 optimization achieves superior pattern fidelity and CD uniformity compared to rule-based windowed correction approaches [4][6].

Predictable Turnaround

Two-tier dynamic workload scheduling maintains <2% execution imbalance across heterogeneous GPU nodes, enabling reliable and consistent job delivery [3].

Industry-Standard Formats

Seamless integration with existing EDA workflows through native support for GDS/OASIS layout files and CD-SEM calibration data.

Complete Correction Workflow

OPC+ integrates three essential modules into a unified, automated pipeline. Each module can be configured independently or combined to match the requirements of a specific fabrication process.

1

OPC Correction

Advanced full-mask inverse lithography with contour-based L2 optimization. Achieves holistic pattern fidelity superior to traditional EPE rule-based correction [4][6].

2

Aerial Image Simulation

High-fidelity imaging simulation incorporating user-defined scanner parameters: exposure wavelength, numerical aperture (NA), spatial resolution, and illumination source configuration [1].

3

Physical Model Calibration

Analytical imaging models fitted to actual lithography process data using CD-SEM measurements. Accounts for scanner-specific, resist, and process variations [4].

flowchart LR A["Upload Layout GDS / OASIS"] --> B["Configure Scanner Parameters"] B --> C{"CD-SEM Calibration Data Available?"} C -->|Yes| D["Physical Model Calibration"] C -->|No| E["GPU-Accelerated ILT Processing"] D --> E E --> F["Global Inverse Optimization"] F --> G["Curvilinear Mask Generation"] G --> H["Download Corrected Mask (GDS / OASIS)"] style A fill:#2E86AB,stroke:#1B6CA8,color:#fff style E fill:#1B998B,stroke:#157A6E,color:#fff style H fill:#E84855,stroke:#C23B45,color:#fff

OPC+ vs. Traditional OPC: A Complete Comparison

A systematic comparison of OPC+ Cloud against conventional on-premises OPC tools across architecture, performance, and business dimensions.

Category Traditional OPC OPC+ Cloud Business Benefit
Mask Geometry SupportManhattan-based (rectilinear only)Native curvilinear and freeformPreserves optical phase and device performance
Design ConversionRequires polygon fracturing / ManhattanizationNo geometry approximation requiredEliminates layout-induced performance loss
Optimization MethodLocal rule-based or windowed EPEGlobal full-mask inverse optimizationHigher pattern fidelity and CD uniformity
GPU UtilizationLimited or static GPU assignmentCost-performance-aware dynamic allocationOptimal cost vs. throughput tradeoff
ParallelismLimited job-level parallelismCUDA Multi-Stream image-level parallelismFaster processing of large layouts
Workload SchedulingStatic or FIFOTwo-tier dynamic schedulingBalanced execution across heterogeneous GPUs
Turnaround PredictabilityVariable, bottleneck-prone<2% execution imbalance across nodesReliable delivery schedules
Deployment ModelOn-premises onlyPublic, private, or hybrid cloudFits foundry security and IT policies
Manufacturing ValidationLogic-centric benchmarksValidated on photonics and metasurfacesProven beyond digital CMOS
Future ReadinessLimited for curvilinear CMOSReady for next-generation curvilinear nodesEnables new process node offerings

How much hardware do you need?

Estimate the GPU fleet to finish OPC on your layout by your deadline — grounded in measured production runs on fully-patterned tiles (2.1 s per correction tile on an RTX 4090; an RTX Pro 6000 runs four isolated MIG workers for ≈1.1 s per tile per card — about 1.9× a 4090). Upload a GDS or OASIS file to auto-detect the die size and pattern density, or set them directly. Everything runs in your browser — your file never leaves your computer.

Your layout
Click or drag & drop — die size and pattern density are detected automatically.
Your file is analyzed locally and never leaves your browser.
Width 16 mm
Height 16 mm
Pixel size 2.6 nm
Production OPC runs 2–5 nm. Finer pixel → far more tiles.
Pattern density 10%
Deadline 3 days
Correction workload
Estimated completion
Prep & assembly
Estimated hardware investment
GPUUnitsFinishTotal $
Unmarked rows are measured on fully-patterned production tiles — sparse, mostly-empty regions run far faster, so these are conservative planning values (4090: 2.10 s per tile, ≈1,700 tiles/hr). Rows marked † are projected from memory bandwidth, which our measurements show governs throughput. The Pro 6000 figure runs each card as four isolated MIG workers (4.49 s per tile per worker → ≈1.1 s per tile per card, about 1.9× the throughput of a 4090). A recommended Pro 6000 node ships fully configured — 96 GB per card, ECC memory, the OPC+ software stack, and support. Treat this as a planning estimate; we confirm the exact figure from a calibration run on your own layout. Hardware prices are indicative market values.

How do I estimate pattern density?

Density is the share of tiles that contain any pattern — not the area your polygons cover. Each tile is 2048 px across, and a tile counts as soon as it holds a single feature. Scattered small structures therefore push density higher than raw area suggests. Uploading your GDS/OASIS file above measures this automatically on the same tile grid the estimator uses. If you can't upload and are unsure, pick the higher band — it's the safer way to size hardware.

If your layout looks like…Use
Isolated test structures or sparse gratings on a mostly empty field1–3%
Labels, alignment marks, a few device blocks on a large die5–10%
Mixed test chip, periodic arrays, photonic device banks10–20%
Dense periodic arrays, metasurface / metalens, full-field patterning60–80%
Rule of thumb: if your pattern is spread across most of the die, you're in the upper bands; if it's concentrated in a small area of a big die, you're in the lower ones. These bands come from measured production layouts — a calibration run on your own file returns the exact figure.

How to Use OPC+ Cloud Platform

Prerequisites

Step-by-Step

  1. Access the Platform
    Navigate to https://opc-cloud.com/ and register an account. The platform supports both English and Traditional Chinese interfaces.
    OPC+ Platform Login Page

    Figure 5. OPC+ web portal login page. Language can be toggled from the top-right menu.

  2. Upload Your Design
    Upload your target layout file (GDS/OASIS) and enter the scanner parameters for your fabrication process.
  3. Configure Calibration (Optional)
    Upload CD-SEM measurement data if physical model calibration is required for your specific fabrication environment.
  4. Submit and Monitor
    Submit your job to the GPU cluster. Track processing progress in real time through the web dashboard.
  5. Download Results
    Retrieve the corrected mask layout (GDS/OASIS), ready for mask writing and manufacturing.

Target Applications

Semiconductor Manufacturing

  • Advanced process node development (7 nm, 5 nm, 3 nm and beyond)
  • Semiconductor foundries and mask shops
  • Fabless design houses
  • Research and development laboratories

Photonic Integrated Circuits

  • Silicon photonic waveguides and ring resonators
  • Apodized grating couplers
  • Metasurfaces and metalenses
  • Curvilinear photonic patterns

Research & Prototyping

  • Rapid design iteration and process exploration
  • Academic research in computational lithography
  • High-volume manufacturing tape-out support

Flexible Deployment Models

OPC+ offers three deployment configurations to accommodate varying security, performance, and budgetary requirements.

Public Cloud

Public Cloud

Managed cluster of 12+ GPUs with optimal job scheduling and resource utilization.

No infrastructure management or maintenance overhead.

Recommended for: Startups, research labs, rapid prototyping
Private Cloud

Private Cloud

Custom on-premises deployment with maximum IP security and data isolation.

Dedicated resources with full administrative control.

Recommended for: Large enterprises, sensitive IP projects
Hybrid Model

Hybrid Model

Combines public and private infrastructure with configurable resource allocation per workload sensitivity.

Balances cost, performance, and data security requirements.

Recommended for: Organizations with variable workload demands

Industry Validation & Partnerships

OPC+ is jointly developed by the Photonics and Advanced Lithography Laboratory (PAL Lab) and the Network and System Laboratory (NSL Lab) at National Yang Ming Chiao Tung University (NYCU). The platform has been validated through collaborative engagements with leading semiconductor and photonics research institutions, bridging cutting-edge academic research in computational lithography with real-world industrial fabrication requirements [3][5].

Taiwan Semiconductor Research Institute (TSRI)
University of Southampton, UK

Supported by the National Science and Technology Council (NSTC), Taiwan.

Demo & Access

OPC+ Cloud Platform

The platform is currently available for research and professional use. Register directly at the platform portal, or contact the team below to discuss access for industrial applications.

https://opc-cloud.com/

Supported by the National Science and Technology Council (NSTC), Taiwan.

References

The following publications document the research and validation underpinning the OPC+ platform.

Foundational References
  • [1] C. Mack, Fundamental Principles of Optical Lithography: The Science of Microfabrication. John Wiley & Sons, 2007.
  • [2] L. Pang, "Inverse lithography technology: 30 years from concept to practical, full-chip reality," Journal of Micro/Nanopatterning, Materials, and Metrology, vol. 20, no. 3, pp. 030901–030901, 2021.
Research Publications
  • [3] S.-Y. Wang et al., "Providing optimal optical proximity correction cloud services for the semiconductor industry," in IEEE International Conference on Cloud Computing Technology and Science (CloudCom), IEEE, 2025.
  • [4] P.-H. Fang and P. Yu, "Tackling data inconsistency and runtime issues in inverse lithography technology (ILT) with comparative convergence study," in DTCO and Computational Patterning III, vol. 12954, SPIE, 2024, p. 129541E.
  • [5] H.-L. Liu et al., "Intelligent proximity correction enabled large-area metasurfaces by KrF photolithography," IEEE Access, vol. 13, pp. 195517–195525, 2025.
  • [6] Y. Shen, N. Wong, and E. Y. Lam, "Level-set-based inverse lithography for photomask synthesis," Optics Express, vol. 17, no. 26, pp. 23690–23701, 2009.
  • [7] K.-H. Wang, P.-H. Fang, and P. Yu, "Practical inverse mask synthesis via data-efficient physics-informed neural networks (PINN) model," in DTCO and Computational Patterning IV, vol. 13425, SPIE, 2025.
  • [8] P.-H. Fang, Y.-S. Chen, J.-S. Wu, and P. Yu, "Inverse reticle optimization with quantum annealing and hybrid solvers," IEEE Access, vol. 12, pp. 33069–33078, 2024.

Get in Touch

Interested in accessing the OPC+ Cloud Platform or exploring research collaboration? Contact the team below.

Principal InvestigatorProf. Peichen Yu
Emailpeichen.yu@nycu.edu.tw
Phone+886-3-5712121 ext. 56357
Platformhttps://opc-cloud.com/
PAL LabPhotonics & Advanced Lithography
NSL LabNetwork and System Laboratory
InstitutionNational Yang Ming Chiao Tung University
AddressNo. 1001 University Road, East District, Hsinchu City 300, Taiwan